Computer processing systems are being increasingly used in real time to processing of video data. In general, these systems include a digitizer which samples an incoming analog video signal, such as an NTSC signal, and converts the sample analog video signal into a suitable digital format. The digitized video data is then provided to a video scaler that scales the digital video data into pixel data which is eventually stored in the host memory and used by the host to recreate images on a display screen, such as a CRT.
Once the pixel data has been generated, it must be interfaced to a data bus on the host processor so that it can be transferred to the host memory. However, there are numerous problems involved in moving continuous flows of real time video data over a host data bus which is operating at a different clock rate and must service requests from other devices. Some of these problems are described in greater detail below with reference to the exemplary PCI data bus.
The PCI bus itself is theoretically capable of moving up to 132 MB/sec, but there are several practical limitations that restrict this transfer rate. Actual PCI implementations have resulted in sustained bandwidths ranging from 24 MB/sec to 118 MB/sec. This performance benchmark is only part of the problem. The specific design of the memory/bus interface is crucial to the efficient transfer of high bandwidth sustained data. Controllers designed to optimize burst operations typically penalize continuous requirements by limiting the duration of time any given device is permitted to access the bus. The addition of bus re-arbitration cycles adds significant latency to the process of transferring image data. This latency poses problems to devices like a video capture adapter that need to stream a continuous flow of data at high speeds.
To compound this, today's video capture PCI interface chips assume that most of the PCI bus bandwidth is available and provide very shallow FIFO's that overflow when the latency in responding to a request becomes large due to other bus activity. The usual recovery mechanism is to discard the contents of the FIFO, reset the DMA pointer to the next valid transfer address, and continue with the transfer from that point. This causes visual artifacts that are very distracting, such as small black strips of pixels that follow any movement in the video image. Previous attempts to alleviate these problems have involved decreasing the necessary bandwidth by scaling down the image and scaling it up with software. However, this also causes degradation in the picture quality.
Another problem occurs due to differing data transfer rates between the incoming video data and the operating speed of the data bus. For example, standard video uses a frequency of 27 MHz while the PCI bus uses a 33 MHz clock. Thus, it is necessary to perform some rate conversion to be able to efficiently transfer data and avoid temporal artifacts.
Another common problem is that today's interface chips assume a large block of contiguous memory is available at the host into which a whole field can be transferred. Modern demand paged operating systems, such as AIX, do not allocate large contiguous blocks of memory. Rather, they partition the memory into discontiguous pages, thus requiring the hardware to change DMA pointers in the middle of a data transfer. It is therefore an object of the present invention to overcome the shortcomings described above. Additional objects and advantages of the present invention will become apparent in view of the following disclosure.